Semiconductor processing methods of forming integrated circuitry

ABSTRACT

Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

TECHNICAL FIELD

[0001] This invention relates generally to semiconductor processingmethods of forming integrated circuitry, and particularly to methods offorming integrated circuit devices having different threshold voltages.

BACKGROUND OF THE INVENTION

[0002] Field effect transistors are characterized by a source region, adrain region and a gate. The source and drain regions are typicallyreceived within a semiconductive material, such as a semiconductivesubstrate. The gate is typically disposed elevationally over the sourceand drain regions. A gate voltage of sufficient minimum magnitude can beplaced on the gate to induce a channel region underneath the gate andbetween the source and drain regions. Such channel-inducing voltage istypically referred to as the transistor's threshold voltage, or V_(t).Accordingly, the threshold voltage turns the transistor on. Once themagnitude of the threshold voltage has been exceeded, current can flowbetween the source and drain regions in accordance with a voltage calledthe source/drain voltage, or V_(ds).

[0003] Threshold voltage magnitudes can be affected by channel implants.Specifically, during fabrication of semiconductor devices, a substratecan be implanted with certain types of impurity to modify or change thethreshold voltage of a resultant device. Such channel implants can alsoaffect a condition known as subsurface punchthrough. Punchthrough is aphenomenon which is associated with a merging of the source and draindepletion regions within a MOSFET. Specifically, as the channel getsshorter (as device dimensions get smaller), depletion region edges getcloser together. When the channel length is decreased to roughly the sumof the two junction depletion widths, punchthrough is established.Punchthrough is an undesired effect in MOSFETS.

[0004] One way of addressing punchthrough in sub-micron devices isthrough provision of a so-called halo implant, also known as a “pocket”implant. Halo implants are formed by implanting dopants (opposite intype to that of the source and drain) within the substrate proximate thesource and drain regions, and are typically disposed underneath thechannel region. The implanted halo dopant raises the dopingconcentration only on the inside walls of the source/drain junctions, sothat the channel length can be decreased without needing to use a higherdoped substrate. That is, punchthrough does not set in until a shorterchannel length because of the halo.

[0005] It is desirable to have MOSFETS with different threshold voltagesdepending upon the context in which the integrated circuitry of whichthey comprise a part is to be used. In the context of memory devices itcan be beneficial to have transistors with different threshold voltages.

[0006] This invention arose out of concerns associated with improvingthe methods through which integrated circuits are fabricated. Inparticular, the invention arose concerns associated with providingimproved methods of forming memory devices.

SUMMARY OF THE INVENTION

[0007] Semiconductor processing methods of forming integrated circuitryare described. In one embodiment, memory circuitry and peripheralcircuitry are formed over a substrate. The peripheral circuitrycomprises first and second type MOS transistors. Second type haloimplants are conducted into the first type MOS transistors in less thanall of the peripheral MOS transistors of the first type. In anotherembodiment, a plurality of n-type transistor devices are formed over asubstrate and comprise memory array circuitry and peripheral circuitry.At least some of the individual peripheral circuitry n-type transistordevices are partially masked, and a halo implant is conducted forunmasked portions of the partially masked peripheral circuitry n-typetransistor devices. In yet another embodiment, at least a portion ofonly one of the source and drain regions is masked, and at least aportion of the other of the source and drains regions is exposed for atleast some of the peripheral circuitry n-type transistor devices. A haloimplant is conducted relative to the exposed portions of the source anddrain regions. In another embodiment, a common masking step is used anda halo implant is conducted of devices formed over a substratecomprising memory circuitry and peripheral circuitry sufficient toimpart to at least three of the devices three different respectivethreshold voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic side sectional view of a semiconductorwafer fragment in process, which is suitable for use in connection withone or more embodiments of the present invention.

[0010]FIG. 2 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.

[0011]FIG. 3 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.

[0012]FIG. 4 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.

[0013]FIG. 5 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.

[0014]FIG. 6 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.

[0015]FIG. 7 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0017] Referring to FIG. 1, a semiconductor wafer fragment in process isshown generally at 10 and includes a semiconductive substrate 12. In thecontext of this document, the term “semiconductive substrate” is definedto mean any construction comprising semiconductive material, including,but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0018] Memory array circuitry 14 and peripheral circuitry 16 are formedover substrate 12. Memory circuitry 14 comprises individual transistors20, 22. Peripheral circuitry 16 comprises a transistor 26. Thesetransistors are shown for example only. Each exemplary transistor willtypically include a conductive gate line 28 (designated for transistors20 and 26 only) having a gate oxide layer 30, a polysilicon layer 32, asilicide layer 34, and an overlying insulative cap 36. Conventionalsidewall spacers SS are optionally provided over the sidewalls of gateline 28. Of course, other gate line constructions could be used.Source/drain regions 37 and 38 are provided within substrate 12.

[0019] The drain regions 37 may be formed in several different ways. Inone embodiment, the drain regions 37 are doped first with a blanketn-minus implant, which may be performed before or after formation of thesidewalls SS. As used herein, the term “blanket implant” refers to animplant process that does not employ a masking step. In one embodiment,the drain regions 37 are doped by out-diffusion of dopants from a dopedpolysilicon layer forming a portion of a storage node 39.

[0020] The source regions 38 may also be formed in several differentways. In one embodiment, the source regions are doped first with ablanket n-minus implant 37′ and then with a n-plus implant, followed bya halo implant 41.

[0021] Typically, the transistors forming peripheral circuitry 16 willinclude first- and second-type MOS transistors. For example and forpurposes of the on-going discussion, first-type MOS transistors willcomprise n-type transistors, and second-type MOS transistors willcomprise p-type transistors. Similarly, in this example, implantscomprising a second-type of material will comprise p-type implants suchas boron.

[0022] Referring to FIGS. 2 and 3, a masking layer 40 is formed oversubstrate 12. Transistor 42 (FIG. 2) can constitute a transistor whichis disposed within the memory array, or one which is disposed within theperipheral area. Similarly, transistor 26 (FIG. 3) can constitute atransistor which is disposed within the memory array, or one which isdisposed within the peripheral area. Transistor 26 can represent one ofmany similar partially-masked transistors in either the peripheral areaor the memory array. In one embodiment, and with masking layer 40 inplace, a second-type halo implant is conducted into transistor 26 and inless than all transistors of the first type. The halo implant forms ahalo region 41 received within substrate 12. In this case, transistor 42can constitute a transistor which does not receive the halo implant. Inone embodiment, when transistors receive the halo implant, only one sideof the transistor receives the implant, such as shown in FIG. 3. Thisconstitutes a different transistor having a different threshold voltageV_(t) than those transistors not receiving the halo implant.

[0023] Specifically, in one embodiment, transistor 26 comprises ann-type transistor device which is partially masked, and the halo implantis conducted for unmasked portions of the transistor or transistors.Various portions of transistor 26 can be masked to result in a partiallymasked transistor. For example, at least a portion of one of the sourceand drain regions can be masked, and at least a portion of the other ofthe source and drain regions can be exposed As a further example, amajority portion of one of the drain regions can be masked, while amajority portion of the other of the source regions is not masked for atleast some of the devices. In the illustrated example, an entirety ofone of the drain regions is masked, and the entirety of the other of thesource regions is not masked. Where a transistor's source region ismasked, after the halo implantation, the transistor will have aconfiguration similar to a source follower configuration. Where atransistor's drain region is masked, after the halo implantation, thetransistor can have its electric field suppressed proximate the drain.

[0024] In another embodiment, the second-type halo implants areconducted into only one of the source and drain regions in less than allof the MOS transistors of the first type, and not the other of thesource and drain regions of those peripheral MOS transistors of thefirst type.

[0025] Referring to FIG. 4, another embodiment of the invention isshown. Leftmost transistor 26 can comprise any of the partially-maskedconfigurations described with respect to FIG. 3. Rightmost transistor 26a has both source and drain regions masked, and constitutes other n-typetransistor devices which do not receive a halo implant. As a result, therightmost transistor 26 a has a lower threshold voltage V_(t) thantransistors receiving the halo implant.

[0026] Referring to FIG. 5, another embodiment of the invention isshown. Leftmost transistor 26 can comprise any of the partially-maskedconfigurations described with respect to FIG. 3. Transistor 26 b hasboth of its source and drain regions left exposed during the haloimplant. Accordingly, halo regions 41 are formed proximate thesource/drain regions of transistor 26 b.

[0027] Referring to FIG. 6, another embodiment of the invention isshown. Leftmost transistor 26 can comprise any of the partially-maskedconfigurations described with respect to FIG. 3. In this embodiment,portions of transistors in either the peripheral or the memory arrayregion are partially masked, and, in addition, the source regions anddrain regions for some other individual transistor devices are masked,e.g. transistor 26 a, while different other individual peripheraltransistor devices, e.g. transistor 26 b, have their source regions anddrain regions exposed during the halo implant. Accordingly, where bothof the source and drain regions are exposed, a pair of halo regions 41is formed. These associated transistor devices having both source anddrain regions exposed are, for purposes of this document, referred to asfirst transistor devices. Where both of the source and drain regions aremasked or otherwise blocked, no halo regions are formed. Theseassociated transistor devices having both source and drain regionsmasked or blocked are, for purposes of this document, referred to assecond transistor devices. Where a portion of a transistor device isexposed, a halo region can, in some instances, be formed with respect toonly one of the source and drain regions. These associated transistordevices are, for purposes of this document, referred to as thirdtransistor devices. Preferably, these associated transistor devices areall NMOS transistor devices.

[0028] Alternately considered, and in a preferred embodiment, a commonmasking step is utilized and in a common implant step, a halo implant isconducted of devices formed over a substrate comprising memory circuitryand peripheral circuitry, sufficient to impart to at least three of thedevices three different respective threshold voltages. In oneembodiment, the three devices comprise NMOS field effect transistors.

[0029] In the context of NMOS field effect transistors in which theimplanted halo impurity comprises a p-type impurity, those transistorswhose source and drain regions are fully exposed, will typically havethe highest threshold voltage V_(t1). Those transistors which arepartially masked during the halo implant will typically have a thresholdvoltage V_(t2) which is somewhat lower than threshold voltage V_(t1).Those transistors whose source and drain regions are completely blockedduring the halo implant will typically have the lowest threshold voltageV_(t3) of the threshold voltages. Accordingly, three different thresholdvoltages are provided through one common masking step.

[0030]FIG. 7 is a side sectional view of a semiconductor wafer fragmentin process in accordance with one embodiment of the invention.Transistors 20 and 22 of FIG. 1 now form memory access transistors 45having a threshold voltage that corresponds to a single halo implant 41on a bitline contact side of the access transistors 45. Storage nodesides 47 of the access transistors 45 are masked by the masking layer 40to prevent boron from being implanted. Forming access transistors 45 inthis way improves refresh capabilities. The one-sided halo implant 41 inthe access transistors 45 allows the channel doping to be reduced whilemaintaining the same threshold voltage V_(t) and subthreshold voltage.The lower channel doping, in turn, gives rise to improved DRAM refreshcharacteristics, because charge leakage from the storage nodes 47 isreduced.

[0031] It will be appreciated that the halo implant and the mask 40therefor may be effectuated before formation of sidewall spacers(denoted “SS” in FIG. 1), as shown in FIGS. 2-7, or after formation ofsidewall spacers (as shown in FIG. 1). The sidewall spacers SS shown inFIG. 1 may be formed using conventional deposition, oxidation and/oretching techniques. It will be appreciated that when boron is implantedinto a n-type device, n-well bias plugs and other conventional featuresshould be masked to avoid compromise of the conductivity of thesefeatures.

[0032] When the halo implant is done with a mask, prior to formation ofsidewall spacers SS, it is normally accompanied by an n-minus implant37, using either phosphorous or arsenic. When the halo implant is doneafter formation of the sidewall spacers SS, it is assumed that then-minus layer 37 was formed earlier as part of a LDD (lightly dopeddrain) structure. This same halo implant is normally accompanied by ann+ source drain implantation.

[0033] One preferred application for such devices can be in the contextof peripheral circuitry comprising a so-called equilibrating device,which is typically connected between bit lines D and D* in dynamicrandom access memory circuitry in order to bring the bit lines to acommon voltage potential (typically V_(cc)/2 ) prior to firing the wordlines to perform a sensing operation. Another application can be for thecross-coupled transistors in a sense amplifier circuit, where lowerthreshold voltage V_(t) is preferred for better margin and refreshproperties. Other applications can include various low-voltageapplications which will be apparent to the skilled artisan.

[0034] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method of forming integrated circuitrycomprising: forming memory circuitry and peripheral circuitry over asubstrate, the peripheral circuitry comprising first and second type MOStransistors; and conducting second type halo implants into the firsttype MOS transistors in less than all peripheral MOS transistors of thefirst type.
 2. The semiconductor processing method of claim 1, whereinthe second type is p-type.
 3. The semiconductor processing method ofclaim 1, wherein the conducting of the second type halo implantscomprises conducting said implants into only one of the source and drainregions in the less than all of the peripheral MOS transistors of thefirst type, and not the other of said source and drain regions of saidless than all of the peripheral MOS transistors of the first type. 4.The semiconductor processing method of claim 1, wherein: the second typeis p-type; and the conducting of the second type halo implants comprisesconducting said implants into only one of the source and drain regionsin the less than all of the peripheral MOS transistors of the firsttype, and not the other of said source and drain regions of said lessthan all of the peripheral MOS transistors of the first type.
 5. In acommon masking step and in a common implant step, conducting a haloimplant of devices formed over a substrate comprising memory circuitryand peripheral circuitry sufficient to impart to at least three of thedevices three different respective threshold voltages.
 6. The method ofclaim 5, wherein said three devices comprise peripheral circuitry. 7.The method of claim 5, wherein said three devices comprise NMOS fieldeffect transistors.
 8. The method of claim 5, wherein said three devicescomprise NMOS field effect transistors comprising peripheral circuitry.9. The method of claim 5, wherein said three devices comprise PMOS fieldeffect transistors.
 10. The method of claim 5, wherein said threedevices comprise PMOS field effect transistors comprising peripheralcircuitry.
 11. The method of claim 5, wherein the common masking stepcomprises masking only portions of some of the devices which receive thehalo implant, said portions comprising portions of peripheral circuitrydevices.
 12. The method of claim 5, wherein: the common masking stepcomprises masking only portions of some of the devices which receive thehalo implant; said devices which receive the halo implant comprise NMOSfield effect transistors; and said portions comprise portions ofperipheral circuitry devices.
 13. The method of claim 5, wherein: thecommon masking step comprises masking only portions of some of thedevices which receive the halo implant; said devices which receive thehalo implant comprise NMOS field effect transistors having sourceregions and drain regions; and said portions comprise portions ofperipheral circuitry devices, wherein said masking comprises maskingonly one of the source region and drain region for one of the threedevices, and exposing both of the source region and drain region foranother of the three devices.
 14. The method of claim 5, wherein: thecommon masking step comprises masking only portions of some of thedevices which receive the halo implant; said devices which receive thehalo implant comprise PMOS field effect transistors; and said portionscomprise portions of peripheral circuitry devices.
 15. The method ofclaim 5, wherein: the common masking step comprises masking onlyportions of some of the devices which receive the halo implant; saiddevices which receive the halo implant comprise PMOS field effecttransistors having source regions and drain regions; and said portionscomprise portions of peripheral circuitry devices, wherein said maskingcomprises masking only one of the source region and drain region for oneof the three devices, and exposing both of the source region and drainregion for another of the three devices.
 16. In a common masking stepand in a common implant step, conducting a halo implant of devicesformed over a substrate comprising memory circuitry and peripheralcircuitry sufficient to impart to at least three of the devices threedifferent respective threshold voltages, at least some of the devicesforming memory access devices.
 17. The method of claim 16, wherein theat least some of the devices forming memory access devices receive haloimplants on a bitline contact side of the devices.
 18. A semiconductorprocessing method of forming integrated circuitry comprising: forming aplurality of n-type transistor devices over a substrate, said n-typedevices comprising memory array circuitry and peripheral circuitry,individual n-type transistor devices having source regions and drainregions; partially masking at least some individual memory array devicesand peripheral circuitry n-type transistor devices; and with said atleast some of the memory array and peripheral circuitry n-typetransistor devices being partially masked, conducting a halo implant forunmasked portions of said at least some peripheral circuitry n-typetransistor devices.
 19. The semiconductor processing method of claim 18,wherein the masking comprises masking storage node portions of one ofthe source region and drain region and not bitline contact portions ofthe other of the source region and drain region for said at least someindividual memory array circuitry n-type transistor devices.
 20. Thesemiconductor processing method of claim 18, wherein the maskingcomprises masking majority portions of one of the source region anddrain region and not majority portions of the other of the source regionand drain region for said at least some individual peripheral circuitryn-type transistor devices.
 21. The semiconductor processing method ofclaim 18, wherein the masking comprises masking one of the source regionand drain region and not the other of the source region and drain regionfor said at least some individual peripheral circuitry n-type transistordevices.
 22. The semiconductor processing method of claim 18, whereinthe masking comprises masking the source regions of said at least someindividual peripheral circuitry n-type transistor devices.
 23. Thesemiconductor processing method of claim 18, wherein the maskingcomprises masking the drain regions of said at least some individualperipheral circuitry n-type transistor devices.
 24. The semiconductorprocessing method of claim 18, wherein the masking comprises (a) maskingportions of only one of the source region and drain region for some ofthe at least some individual peripheral circuitry n-type transistordevices, and also (b) masking both source regions and drain regions forother individual peripheral circuitry n-type transistor devices.
 25. Thesemiconductor processing method of claim 24, wherein said masking of theportions of only one of the source region and drain region comprisesmasking an entirety of said portions of only one of the source regionand drain region for said at least some individual peripheral circuitryn-type transistor devices.
 26. The semiconductor processing method ofclaim 18, wherein the masking comprises (a) masking portions of only oneof the source region and drain region for some of the at least someindividual peripheral circuitry n-type transistor devices, and also (b)leaving source regions and drain regions exposed for other individualperipheral circuitry n-type transistor devices.
 27. The semiconductorprocessing method of claim 18, wherein the masking comprises (a) maskingportions of only one of the source region and drain region for some ofthe at least some individual peripheral circuitry n-type transistordevices, and also (b) masking both source regions and drain regions forother individual peripheral circuitry n-type transistor devices, and (c)leaving source regions and drain regions exposed for different otherindividual peripheral circuitry n-type transistor devices.
 28. Asemiconductor processing method of forming integrated circuitrycomprising: forming a plurality of n-type transistor devices over asubstrate comprising memory array circuitry and peripheral circuitry,individual n-type transistor devices having source regions and drainregions; masking at least a portion of one of the source and drainregions for at least some of the peripheral circuitry n-type transistordevices, and exposing at least a portion of the other of the source anddrain regions for said at least some peripheral circuitry n-typetransistor devices; and conducting a halo implant of the exposedportions of the other of the source and drain regions.
 29. Thesemiconductor processing method of claim 28, wherein the maskingcomprises masking the entire portion of the one source and drain regionfor said at least some of the peripheral circuitry n-type transistordevices.
 30. The semiconductor processing method of claim 28, whereinthe masking comprises exposing the entire portion of the other of saidsource and drain regions for said at least some peripheral circuitryn-type transistor devices.
 31. The semiconductor processing method ofclaim 28, wherein the masking comprises: masking the entire portion ofthe one source and drain region for said at least some of the peripheralcircuitry n-type transistor devices; and exposing the entire portion ofthe other of said source and drain regions for said at least someperipheral circuitry n-type transistor devices.
 32. The semiconductorprocessing method of claim 28, wherein the masking comprises alsomasking both source regions and drain regions for other peripheralcircuitry n-type transistor devices.
 33. The semiconductor processingmethod of claim 28, wherein the masking comprises leaving both sourceregions and drain regions for other peripheral circuitry n-typetransistor devices exposed.
 34. The semiconductor processing method ofclaim 28, wherein the masking comprises: also masking both sourceregions and drain regions for other peripheral circuitry n-typetransistor devices; and leaving both source regions and drain regionsfor different other peripheral circuitry n-type transistor devicesexposed.
 35. The semiconductor processing method of claim 28, whereinthe masking comprises: masking the entire portion of the one source anddrain region for said at least some of the peripheral circuitry n-typetransistor devices; also masking both source regions and drain regionsfor other peripheral circuitry n-type transistor devices; and leavingboth source regions and drain regions for different other peripheralcircuitry n-type transistor devices exposed.
 36. The semiconductorprocessing method of claim 28, wherein the masking comprises: maskingthe entire portion of the one source and drain region for said at leastsome of the peripheral circuitry n-type transistor devices; exposing theentire portion of the other of said source and drain regions for said atleast some peripheral circuitry n-type transistor devices; also maskingboth source regions and drain regions for other peripheral circuitryn-type transistor devices; and leaving both source regions and drainregions for different other peripheral circuitry n-type transistordevices exposed.
 37. A semiconductor processing method of formingintegrated circuitry comprising: forming a plurality of NMOS fieldeffect transistor devices over a substrate comprising memory arraycircuitry and peripheral circuitry, individual NMOS transistor deviceshaving source regions and drain regions; forming a mask over thesubstrate, the mask (a) exposing source and drain regions of first NMOStransistor devices, (b) covering source and drain regions of second NMOStransistor devices, and (c) partially exposing only a portion of thirdNMOS transistor devices; and with the mask in place, conducting a haloimplant.
 38. The semiconductor processing method of claim 37, whereinthe forming of the mask to partially expose only a portion of the thirdNMOS transistor devices comprises exposing an entirety of one of thesource and drain regions and not an entirety of the other of the sourceand drain regions for the third NMOS transistor devices.
 39. Thesemiconductor processing method of claim 37, wherein the forming of themask to partially expose only a portion of the third NMOS transistordevices comprises exposing one of the source and drain regions and notthe other of the source and drain regions for the third NMOS transistordevices.
 40. The semiconductor processing method of claim 37, whereinthe forming of the mask to partially expose only a portion of the thirdNMOS transistor devices comprises exposing a portion of one of thesource and drain regions and not the other of the source and drainregions for the third NMOS transistor devices.
 41. A method of improvingDRAM storage cell retention time comprising conducting, in a commonmasking step and in a common implant step, a halo implant of devicesformed over a substrate comprising memory circuitry and peripheralcircuitry sufficient to impart to each device one of two or moredifferent respective threshold voltages, at least some of the devicesforming memory access devices, wherein the at least some of the devicesforming memory access devices receive halo implants on a bit linecontact side of the devices.
 42. The method of claim 41 wherein the haloimplant is performed prior to formation of sidewall spacers in thememory access devices.
 43. The method of claim 41 wherein the halo.implant is performed after formation of sidewall spacers in the memoryaccess devices.
 44. The method of claim 41 wherein the halo implant isaccompanied with an n-minus implant on the bit line contact side. 45.The method ov claim 41 wherein the storage node side of the memoryaccess device is masked from the halo implant.
 46. A method of improvingDRAM storage cell retention time comprising forming memory accessdevices having different implants and hence different junctionstructures on a bitline contact side and a storage node siderespectively.
 47. The method of claim 46 wherein forming memory accessdevices includes: performing, during a masking and implant step, aone-sided halo implant on the bitline contact side; and performing,during the masking and implant step, an n-minus implant on the bitlinecontact side.
 48. The method of claim 47, wherein performing a one-sidedhalo implant is performed prior to formation of sidewall spacers. 49.The method of claim 46, wherein the. storage node side is masked duringa one-sided halo implant on the bitline contact side.